Three-dimensional integrated device

Abstract

A three-dimensional integrated device includes at least two integrated circuit substrates laminated to each other, each of the integrated circuit substrates having at least one ground plane, at least one aperture provided at a desired location in the ground plane, the end of a microstrip line formed in a pair with the ground plane and placed in the aperture, and a transmitter and/or a receiver that is connected to the microstrip line and transmits and/or receives signals at a frequency substantially corresponding to the perimeter λ of the aperture. Each of the apertures in each of the integrated circuit substrates is superimposed on at least one of the apertures in the other integrated circuit substrates in the direction perpendicular to the ground planes, and the signals are transported in a contactless manner between the integrated circuit substrates through the apertures at a frequency substantially corresponding to the perimeter λ of the apertures.

Claims

1 . A three-dimensional integrated device comprising: at least two integrated circuit substrates laminated to each other, each of the integrated circuit substrates having at least one ground plane, at least one aperture provided at a desired location in the ground plane, the end of a microstrip line formed in a pair with the ground plane and placed in the aperture, and a transmitter and/or a receiver that is connected to the microstrip line and transmits and/or receives signals at a frequency substantially corresponding to the perimeter λ of the aperture, wherein each of the apertures in each of the integrated circuit substrates is superimposed on at least one of the apertures in the other integrated circuit substrates in the direction perpendicular to the ground planes, and the signals are transported in a contactless manner between the integrated circuit substrates through the apertures at a frequency substantially corresponding to the perimeter λ of the apertures. 2 . The three-dimensional integrated device according to claim 1 , wherein at least one of the integrated circuit substrates has a pattern formed therein, the pattern having a periodic structure created according to a genetic algorithm, and the period of the pattern is about λ/4. 3 . The three-dimensional integrated device according to claim 2 , wherein the periodic structure, is formed at the bottom of the silicon substrate, and the pattern in a conductive portion of the silicon substrate is created by utilizing the change in carrier concentration of the silicon substrate itself. 4 . The three-dimensional integrated device according to claim 1 , wherein one end of the microstrip line connected to the transmitter and one end of the microstrip line connected to the receiver are formed in each of the apertures, and when one of the integrated circuit substrates functions as the signal transmission side, the other integrated circuit substrates function as the reception side. 5 . The three-dimensional integrated device according to claim 1 , wherein each of the integrated circuit substrates has an aperture where one end of the microstrip line connected to the transmitter is formed and an aperture where one end of the microstrip line connected to the receiver is formed, and each of the integrated circuit substrates functions as the signal transmission side and the signal reception side, so that one of the integrated circuit substrates successively transports signals to the other integrated circuit substrates. 6 . The three-dimensional integrated device according to claim 1 , wherein each of the integrated circuit substrates is formed of a silicon substrate having at least one through via for power supply and ground wiring, and the integrated circuit substrates are laminated to each other through bumps electrically connected to the through via.
CROSS REFERENCES TO RELATED APPLICATIONS [0001] The present invention contains subject matter related to Japanese Patent Application JP 2006-069545 filed in the Japanese Patent Office on Mar. 14, 2006, the entire contents of which being incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to a three-dimensional integrated device formed of a plurality of integrated circuit substrates laminated to each other, and particularly to a three-dimensional integrated device suitably used in a system that integrates various functions, such as a memory CPU function, an imaging element and signal processing device function, and a communication function. [0004] 2. Description of the Related Art [0005] In recent years, due to the advance of high integration and acceleration in operating frequency of LSIs along with increase in the number of I/O lines in the LSIs, various problems have become increasingly serious, such as limitation of wiring physical signal lines, degradation of signal quality (degradation of waveforms) and increase in power consumption in signal I/O sections. [0006] The following approaches using electromagnetic waves have been investigated: (1) Approach in which an antenna is provided on a chip (for example, see 2005 IEEE International Solid-State Circuits Conference Proceedings, Atsushi Iwata, Mamoru Sasaki, Takamaro Kikkawa, Seiji Kameda, Hiroshi Ando, Kentaro Kimoto, Daisuke Arizono, Hideo Sunami, “A 3D Integration Scheme utilizing Wireless Interconnections for Implementing Hyper Brains”, 2005 IEEE International Solid-State Circuits Conference, pp. 262-263, which is hereinafter referred to as the non-patent document 1) (2) Approach in which electromagnetic coupling between inductors is used (for example, see 2005 IEEE International Solid-State Circuits Conference Proceedings, Noriyuki Miura 1 , Daisuke Mizoguchi 1 , Mari Inoue 1 , Hiroo Tsuji 1 , Takayasu Sakurai 2 , Tadahiro Kuroda 1 , “A 195 GB/s 1.2 W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme”, 2005 IEEE International Solid-State Circuits Conference, pp. 264-265, which is hereinafter referred to as the non-patent document 2) (3) Method in which capacitor coupling using opposing pads is used (for example, see 2005 IEEE International Solid-State Circuits Conference Proceedings, Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Paul D. Franzon, “3 Gb/s AC-Coupled Chip-to-Chip Communication using a Low-Swing Pulse Receiver”, 2005 IEEE International Solid-State Circuits Conference, pp. 522-523, which is hereinafter referred to as the non-patent document 3) SUMMARY OF THE INVENTION [0010] However, the approach in which an antenna is provided on a chip as described in the non-patent document 1 has a fundamental problem that the output originated from one LSI via the antenna disadvantageously induces a current in wiring in the LSI. The method described in the non-patent document 3 can work with coupling corresponding to two LSIs, but has difficulty in reliably extending to the case where three or more LSIs are laminated or a problem of increased power consumption depending on the size of the capacitor. The non-patent document 2 has a problem of interference between vertically or horizontally adjacent inductors. [0011] Furthermore, when the thus configured three-dimensional LSI is mounted on a board, there is a problem of unnecessary emission toward other LSIs mounted on the board, wiring on the board or the outside of the apparatus in which the three-dimensional LSI is mounted. [0012] In view of the above problems of the related art, it is desirable to solve a number of problems associated with the connection between multi-pin and small-pitched LSIs. [0013] It is also desirable to solve the problems of interference on a LSI, interference between wireless channels as well as interference with other LSIs and wiring on a board, which have been the biggest problems for wireless connection. [0014] Other objects of the invention and specific advantages obtained therefrom will become more apparent from the following description of embodiments. [0015] A three-dimensional integrated device according to an embodiment of the invention includes at least two integrated circuit substrates laminated to each other, each of the integrated circuit substrates having at least one ground plane, at least one aperture provided at a desired location in the ground plane, the end of a microstrip line formed in a pair with the ground plane and placed in the aperture, and a transmitter and/or a receiver that is connected to the microstrip line and transmits and/or receives signals at a frequency substantially corresponding to the perimeter λ of the aperture. Each of the apertures in each of the integrated circuit substrates is superimposed on at least one of the apertures in the other integrated circuit substrates in the direction perpendicular to the ground planes. The signals are transported in a contactless manner between the integrated circuit substrates through the apertures at a frequency substantially corresponding to the perimeter λ of the apertures. [0016] In the three-dimensional integrated device according to the embodiment of the invention, at least one of the integrated circuit substrates has a pattern formed therein, the pattern having a periodic structure created according to a genetic algorithm. The period of the pattern is about λ/4. [0017] In the three-dimensional integrated device according to the embodiment of the invention, the periodic structure is formed at the bottom of the silicon substrate, and the pattern in a conductive portion of the silicon substrate is created by utilizing the change in carrier concentration of the silicon substrate itself. [0018] In the three-dimensional integrated device according to the embodiment of the invention, one end of the microstrip line connected to the transmitter and one end of the microstrip line connected to the receiver are formed in each of the apertures, and when one of the integrated circuit substrates functions as the signal transmission side, the other integrated circuit substrates function as the reception side. [0019] In the three-dimensional integrated device according to the embodiment of the invention, each of the integrated circuit substrates has an aperture where one end of the microstrip line connected to the transmitter is formed and an aperture where one end of the microstrip line connected to the receiver is formed. Each of the integrated circuit substrates functions as the signal transmission side and the signal reception side, so that one of the integrated circuit substrates successively transports signals to the other integrated circuit substrates. [0020] In the three-dimensional integrated device according to the embodiment of the invention, each of the integrated circuit substrates is formed of a silicon substrate having at least one through via for power supply and ground wiring, and the integrated circuit substrates are laminated to each other through bumps electrically connected to the through via. [0021] According to an embodiment of the invention, a simple circuit can be used to transport signals between the chips on laminated LSIs without metallic bonding, thereby solving a number of problems associated with the connection between multi-pin and small-pitched LSIs. [0022] For example, it is possible to significantly enhance the reliability of signal I/O between laminated chips, which otherwise suffer from increasingly higher connection cost and increasingly reduced reliability. [0023] While it is necessary to give consideration to the problems, such as signal integrity at I/O sections in LSIs operating at higher speed, wireless configuration can significantly reduce the number of implementation design steps. [0024] The tree-dimensional configuration using wireless transportation described above can be achieved at significantly low cost without costly processes, such as bump formation and through hole formation. The three-dimensional configuration can also significantly reduce the length of signal lines between LSI chips, so that wiring load and power consumption at I/O sections can be reduced. Furthermore, the three-dimensional configuration is significantly advantageous in terms of signal transportation distortion. [0025] According to the embodiments of the invention, it is possible to solve the problems of interference on a LSI, interference between wireless channels as well as interference with other LSIs and wiring on a board, which have been the biggest problems in wireless connection of related art. BRIEF DESCRIPTION OF THE DRAWINGS [0026] FIG. 1 is a perspective view diagrammatically showing an exemplary configuration of the three-dimensional integrated device to which the invention is applied; [0027] FIG. 2 is a perspective view diagrammatically showing another exemplary configuration of the three-dimensional integrated device to which the invention is applied; [0028] FIGS. 3A and 3B diagrammatically show a PBG structure formed on a silicon substrate; [0029] FIG. 4 is a cross-sectional view diagrammatically showing still another exemplary configuration of the three-dimensional integrated device to which the invention is applied; and [0030] FIG. 5 is a cross-sectional view diagrammatically showing still another exemplary configuration of the three-dimensional integrated device having a PBG structure to which the invention is applied. DESCRIPTION OF THE PREFERRED EMBODIMENTS [0031] Embodiments of the invention will be described below in detail with reference to the drawings. The invention is of course not limited to the following examples but changes can be arbitrarily made as far as they do not depart from the spirit of the invention. [0032] The invention is applied to a three-dimensional integrated device 10 , for example, configured as shown in FIG. 1 . [0033] The three-dimensional integrated device 10 shown in FIG. 1 includes two integrated circuit substrates 17 A and 17 B laminated to each other, each of which is formed of a silicon substrate. Each of the integrated circuit substrates 17 A and 17 B has one ground plane, that is ground planes 11 A and 11 B, as well as one aperture, that is apertures 12 A and 12 B provided at desired locations in the ground planes 11 A and 11 B. The integrated circuit substrates 17 A and 17 B also have open ends of microstrip lines 13 A and 13 B formed in pairs with the ground planes 11 A and 11 B and placed in the apertures 12 A and 12 B, and transmitters 15 A, 15 B and receivers 16 A, 16 B that are selectively connected to the microstrip lines 13 A and 13 B via switches 14 A and 14 B and transmit and receive signals at a frequency substantially corresponding to the perimeter λ of the apertures 12 A and 12 B. The apertures 12 A and 12 B in the integrated circuit substrates 17 A and 17 B are disposed at the locations where the apertures are superimposed on each other in the direction perpendicular to the ground planes 11 A and 11 B. [0034] In the thus configured three-dimensional integrated device 10 , the apertures 12 A and 12 B where the open ends of the microstrip lines 13 A and 13 B are located function as so-called slot antennas, so that the transmitters 15 A, 15 B and receivers 16 A, 16 B can be used to transport signals in a contactless manner between the integrated circuit substrates 17 A and 17 B through the apertures 12 A and 12 B at the frequency substantially corresponding to the perimeter λ of the apertures 12 A and 12 B. [0035] That is, in the three-dimensional integrated device 10 , the microstrip lines 13 A, 13 B and the apertures 12 A, 12 B where the open ends of the microstrip lines 13 A, 13 B are located function as communication elements that transmit and receive signals at the frequency substantially corresponding to the perimeter λ of the apertures 12 A and 12 B. [0036] The communication elements is configured to resonate at a frequency corresponding to the perimeter λ of the apertures 12 A and 12 B in the ground planes 11 A and 11 B (λ e =λ/√(ε×μ), where ε and μ are the dielectric constant and the magnetic permeability of the medium, respectively) and are particularly useful in the microwave band (approximately higher than 5 GHz) or higher. [0037] The apertures 12 A and 12 B may have an elongated slit-like shape or a rectangular shape, or may have no definite shape. When the effective dielectric constant and magnetic permeability of the dielectric material that forms the apertures are both 4.1 and the shape is a square, the length of one side of the square is about 3.75 mm for a transmission frequency of 10 GHz, 1.25 mm for 30 GHz and 0.625 mm for 60 GHz. A plurality of such communication elements can be juxtaposed on the LSI. [0038] By juxtaposing a plurality of the communication elements on the LSI, for example, as shown in FIG. 2 , a three-dimensional integrated device 20 having a wireless shared-bus configuration can be formed. [0039] The three-dimensional integrated device 20 shown in FIG. 2 includes four integrated circuit substrates 27 A, 27 B, 27 C and 27 D laminated to each other. Each of the integrated circuit substrates 27 A, 27 B, 27 C and 27 D have one ground plane, that is ground planes 21 A, 21 B, 21 C and 21 D, respectively. The integrated circuit substrates 27 A, 27 B, 27 C and 27 D also have three apertures 22 A 1 to 22 A 3 , 22 B 1 to 22 B 3 , 22 C 1 to 22 C 3 and 22 D 1 to 22 D 3 provided at desired locations in the ground planes 21 A, 21 B, 21 C and 21 D, open ends of two microstrip lines formed in pairs with the ground planes 21 A, 21 B, 21 C and 21 D and placed in the apertures 22 A 1 to 22 A 3 , 22 B 1 to 22 B 3 , 22 C 1 to 22 C 3 and 22 D 1 to 22 D 3 , that is, 23 A 1A , 23 A 1B to 23 A 3A , 23 A 3B ; 23 B 1A , 23 B 1B to 23 B 3A , 23 B 3B ; 23 C 1A , 23 C 1B to 23 C 3A , 23 C 3B ; and 23 D 1A , 23 D 1B to 23 D 3A , 23 D 3B , and transmitters 25 A 1A to 25 A 3A , 25 B 1A to 25 B 3A , 25 C 1A to 25 C 3A and 25 D 1A to 25 D 3A that are connected to the microstrip lines 23 A 1A to 23 A 3A , 23 B 1A to 23 B 3A , 23 C 1A to 23 C 3A and 23 D 1A to 23 D 3A and transmit signals at a frequency substantially corresponding to the perimeter λ of the apertures 22 A 1 to 22 A 3 , 22 B 1 to 22 B 3 , 22 C 1 to 22 C 3 and 22 D 1 to 22 D 3 and receivers 26 A 1A to 26 A 3A , 26 B 1A to 26 B 3A , 26 C 1A to 26 C 3A and 26 D 1A to 26 D 3A that are connected to the microstrip lines 23 A 1B to 23 A 3B , 23 B 1B to 23 B 3B , 23 C 1B to 23 C 3B and 23 D 1B to 23 D 3B and receive signals at the frequency substantially corresponding to the perimeter λ of the apertures 22 A 1 to 22 A 3 , 22 B 1 to 22 B 3 , 22 C 1 to 22 C 3 and 22 D 1 to 22 D 3 . The apertures 22 A 1 to 22 A 3 , 22 B 1 to 22 B 3 , 22 C 1 to 22 C 3 and 22 D 1 to 22 D 3 in the integrated circuit substrates 27 A, 27 B, 27 C and 27 D are disposed at the locations where the apertures are superimposed on each other in the direction perpendicular to the ground planes 21 A, 21 B, 21 C and 21 D. [0040] The integrated circuit substrates 27 A, 27 B, 27 C and 27 D are formed of silicon substrates having at least one through vias (not shown) for power supply and ground wiring. The integrated circuit substrates 27 A, 27 B, 27 C and 27 D are laminated to each other with interposed bumps 28 electrically connected to the through vias. [0041] In the three-dimensional integrated device 20 configured as shown in FIG. 2 , the integrated circuit substrates 27 A, 27 B, 27 C and 27 D are configured such that the three sets 22 A 1 to 22 D 1 , 22 A 2 to 22 D 2 and 22 A 3 to 22 D 3 vertically superimposed on each other function as communication channels A, B and C, each of which is capable of individually sending and receiving signals. For example, when the transmitters 25 A 1A to 25 A 3A of the integrated circuit substrate 27 A are turned on, any one of the receivers 26 B 1A to 26 B 3A , 26 C 1A to 26 C 3A or 26 D 1A to 26 D 3A of the integrated circuit substrates 27 B, 27 C and 27 D can be turned on to receive the signal originated from the integrated circuit substrate 27 A at the integrated circuit substrate that has been turned on. Alternatively, when the transmitters 25 A 1A to 25 A 3A of the integrated circuit substrate 27 A are turned on, all receivers 26 B 1A to 26 B 3A , 26 C 1A to 26 C 3A and 26 D 1A to 26 D 3A of the integrated circuit substrates 27 B, 27 C and 27 D can be turned on. In this case, the integrated circuit substrates 27 B, 27 C and 27 D can be operated in a simultaneous reception mode and hence in a BUS operation mode of related art. [0042] Moreover, the three sets of communication channels A, B and C in the three-dimensional integrated device 20 can independently send and receive signals. [0043] The three-dimensional integrated device 20 can be mounted on a circuit substrate 30 having one ground plane 31 , three apertures 32 A 1 to 32 A 3 provided at desired locations in the ground plane 31 , open ends of two microstrip lines 33 A 1A and 33 A 1B formed in a pair with the ground plane 31 and placed in the apertures 32 A 1 to 32 A 3 , and transmitters 35 A 1A to 35 A 3A that are connected to the microstrip line 33 A 1A and transmit signals at a frequency substantially corresponding to the perimeter λ of the apertures 32 A 1 to 32 A 3 and receivers 36 A 1A to 36 A 3A that are connected to the microstrip line 33 A 1B and receive signals at the frequency substantially corresponding to the perimeter λ of the apertures 32 A 1 to 32 A 3 , so as to use the three sets of communication channels A, B and C to send and receive signals between the circuit substrate 30 and the integrated circuit substrates 27 A, 27 B, 27 C and 27 D. [0044] Although in the three-dimensional integrated device 20 shown in FIG. 2 , two microstrip lines are disposed in one aperture and connected to the transmitters and receivers, respectively, a switch provided in the LSI is used to share one microstrip line, as in the three-dimensional integrated device 10 shown in FIG. 1 . [0045] In the three-dimensional integrated device 20 shown in FIG. 2 , other circuits provided on the integrated circuit substrates 27 A, 27 B, 27 C and 27 D are isolated in terms of electric emission by the ground planes 21 A, 21 B, 21 C and 21 D, minimizing interlayer crosstalk. [0046] However, in the configuration shown in FIG. 2 , the ground planes 21 A, 21 B, 21 C and 21 D may shield near-field electric fields but may not shield near-field magnetic fields. [0047] To address this problem, as shown in FIGS. 3A and 3B , the silicon substrate 27 that forms each of the laminated integrated circuit substrates 27 A, 27 B, 27 C and 27 D is used to configure a PBG (Photonic Band Gap) (or EBG; Electronic Band Gap) structure so as to shield the magnetic field as well. [0048] Although a conductive silicon substrate inherently absorbs electromagnetic waves in a high frequency region, it is fortunately possible to use diffusion or ion implantation to create a P+ or N+ layer in a transistor formation process. [0049] In this case, although the base substrate is desirably a high-resistance substrate, a P+ or N+ layer can be used to create a periodic structure having the same period as that of the communication wavelength on the back side of the substrate, as shown in FIGS. 3A and 3B , allowing formation of EBG. By particularly removing such structures at the portions corresponding to the communication elements of the laminated integrated circuit substrates, it is possible to enhance only partial coupling and suppress the leak of the magnetic field to unnecessary portions. [0050] To create the PBG structure shown in FIGS. 3A and 3B , firstly, for example, a diffusion process or an ion implantation process is used to create the illustrated periodic structure, that is, a conductive layer 29 A, on a desired surface of the silicon substrate 27 . [0051] Then, RIE (anisotropic etching) or the like is used to form through vias 29 B in the silicon substrate 27 . Thereafter, CVD or the like is used to coat the inner surfaces of the vias with insulating films as appropriate. Furthermore, plating or the like is used to make the inner surfaces of the vias conductive. [0052] In this case, the silicon substrate 27 is desirably a high-resistance substrate, and the conductive through vias 29 B are connected to the power supply or the ground on the integrated circuit substrate. [0053] Thus, the silicon substrate 27 having the periodic structure 29 , that is, the conductive layer 29 A provided with the conductive through vias 29 B, can be configured to shield a magnetic field. [0054] In the example shown in FIG. 3 , although diffusion or ion implantation is used to create the P+ or N+ layer or the like, the periodic structure may of course be created by depositing metal, such as Au, Cu and Al, on the back side. [0055] In the three-dimensional integrated device 20 shown in FIG. 2 , although the description has been made of the configuration of the integrated circuit substrates 27 A, 27 B, 27 C and 27 D in which the three sets 22 A 1 to 22 D 1 , 22 A 2 to 22 D 2 and 22 A 3 to 22 D 3 vertically superimposed on each other function as communication channels A, B and C, each of which is capable of individually sending and receiving signals, the invention can be applied to a three-dimensional integrated device 40 having a ring bus configuration, as shown in FIG. 4 . [0056] The ring bus configuration of the three-dimensional integrated device 40 shown in FIG. 4 is obtained by sharing two apertures in integrated circuit substrates of four integrated circuit substrates 47 A, 47 B, 47 C and 47 D and successively sending and receiving signals between the integrated circuit substrates. [0057] That is, the three-dimensional integrated device 40 includes the four integrated circuit substrates 47 A, 47 B, 47 C and 47 D laminated to each other. Each of the integrated circuit substrates 47 A, 47 B, 47 C and 47 D have one ground plane, that is, ground planes 41 A, 41 B, 41 C and 41 D, respectively. The integrated circuit substrates 47 A, 47 B, 47 C and 47 D also have two to four apertures 42 A 1 , 42 A 2 , 42 B 1 to 42 B 4 , 42 C 1 to 42 C 4 and 42 D 1 , 42 D 2 provided at desired locations in the ground planes 41 A, 41 B, 41 C and 41 D, open ends of microstrip lines 43 A 1 , 43 A 2 , 43 B 1 to 43 B 4 , 43 C 1 to 43 C 4 , and 43 D 1 , 43 D 2 formed in pairs with the ground planes 41 A, 41 B, 41 C and 41 D and placed in the apertures 42 A 1 , 42 A 2 , 42 B 1 to 42 B 4 , 42 C 1 to 42 C 4 and 42 D 1 , 42 D 2 , and transmitters 45 A, 45 B 2 , 45 B 1 , 45 C 1 , 45 C 2 , 45 D that are connected to the microstrip lines 43 A 1 , 43 B 2 , 43 B 3 , 43 C 1 , 43 C 4 and 43 D 2 and transmit signals at a frequency substantially corresponding to the perimeter λ of the apertures 42 A 1 , 42 B 2 , 42 B 3 , 42 C 1 , 42 C 4 and 42 D 2 and receivers 46 A, 46 B 1 , 46 B 2 , 46 C 2 , 46 C 1 and 46 D that are connected to the microstrip lines 43 A 2 , 43 B 1 , 43 B 4 , 43 C 2 , 43 D 3 and 43 D 1 and receive signals at a frequency substantially corresponding to the perimeter k of the apertures 42 A 2 , 42 B 1 , 42 B 4 , 42 C 2 , 42 C 3 and 42 D 1 . The apertures 42 A 1 , 42 A 2 in the integrated circuit substrate 47 A and the apertures 42 B 1 , 42 B 2 in the integrated circuit substrate 47 B, the apertures 42 B 3 , 42 B 4 in the integrated circuit substrate 47 B and the apertures 42 C 3 , 42 C 4 in the integrated circuit substrate 47 C, the apertures 42 C 1 , 42 C 2 in the integrated circuit substrate 47 C and the apertures 42 D 1 , 42 D 2 in the integrated circuit substrate 47 D are disposed at the locations where the apertures of above respective combinations are superimposed on each other in the direction perpendicular to the ground planes 41 A, 41 B, 41 C and 41 D. [0058] In the thus configured three-dimensional integrated device 40 , transmission slots and reception slots are basically distinguished from each other. For example, the integrated circuit substrates 47 C and 47 D use a slot A to send signals from the integrated circuit substrate 47 D to the integrated circuit substrate 47 C, while a slot B is used to send signals from the integrated circuit substrate 47 C to the integrated circuit substrate 47 D. [0059] By successively repeating this configuration upward and downward as shown in FIG. 4 , a three-dimensional integrated device having a ring bus configuration is achieved. [0060] Furthermore, also in the three-dimensional integrated device 40 having such a ring bus configuration, as shown in FIG. 5 , by creating the periodic structure 29 , that is, the conductive layer 29 A provided with the conductive through vias 29 B in the silicon substrates that form the integrated circuit substrates 47 A, 47 B, 47 C and 47 D, as in the PBG structure shown in FIGS. 3A and 3B , near-field magnetic fields can be shielded. By removing the PBG structures at the portions corresponding to the apertures 42 A 1 , 42 A 2 , 42 B 1 to 42 B 4 , 42 C 1 to 42 C 4 and 42 D 1 , 42 D 2 in the integrated circuit substrates 47 A, 47 B, 47 C and 47 D, signals can be satisfactorily transported. Since the PBG structure suppresses dispersion of magnetic fields, interference between the channels and interference with the wiring on the integrated circuit substrate is suppressed, and interference with the wiring on the board on which the integrated circuit device is mounted and interference with other integrated circuit substrates can also be suppressed. [0061] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (10)

    Publication numberPublication dateAssigneeTitle
    US-2005156755-A1July 21, 2005Formfactor, Inc.Electromagnetically coupled interconnect system architecture
    US-2006076658-A1April 13, 2006Advanced Semiconductor Engineering, Inc.Semiconductor package structure with microstrip antennan
    US-5872545-AFebruary 16, 1999Agence Spatiale EuropeenePlanar microwave receive and/or transmit array antenna and application thereof to reception from geostationary television satellites
    US-6087989-AJuly 11, 2000Samsung Electronics Co., Ltd.Cavity-backed microstrip dipole antenna array
    US-6333552-B1December 25, 2001Sharp Kabushiki KaishaMillimeter wave semiconductor device
    US-6535090-B1March 18, 2003Mitsubishi Denki Kabushiki KaishaCompact high-frequency circuit device
    US-6717229-B2April 06, 2004Fabtech, Inc.Distributed reverse surge guard
    US-6888420-B2May 03, 2005Hrl Laboratories, LlcRF MEMS switch matrix
    US-6998708-B2February 14, 2006Xytrans, Inc.Millimeter wave (MMW) transceiver module with transmitter, receiver and local oscillator frequency multiplier surface mounted chip set
    US-7045901-B2May 16, 2006Megic CorporationChip-on-chip connection with second chip located in rectangular open window hole in printed circuit board

NO-Patent Citations (0)

    Title

Cited By (16)

    Publication numberPublication dateAssigneeTitle
    CN-102592166-AJuly 18, 2012索尼公司信号传输设备、电子设备以及信号传输方法
    CN-104937768-ASeptember 23, 2015韩国科学技术院使用介质波导的低功率、高速多通道芯片到芯片接口
    US-2006232949-A1October 19, 2006Hideki OsakaMain board for backplane buses
    US-2009218407-A1September 03, 2009Broadcom CorporationIntegrated circuit with millimeter wave and inductive coupling and methods for use therewith
    US-2011026234-A1February 03, 2011Samsung Electro-Mechanics Co., Ltd.Printed circuit board and electro application
    US-2011158344-A1June 30, 2011Sony CorporationIn-millimeter-wave dielectric transmission device and method for manufacturing same, and wireless transmission device and wireless transmission method
    US-2012087521-A1April 12, 2012Analog Devices, Inc.Microphone Package with Embedded ASIC
    US-2013229779-A1September 05, 2013Sansung Electro-Mechanics Co., Ltd.Printed circuit board and electro application
    US-7505285-B2March 17, 2009Hitachi, Ltd.Main board for backplane buses
    US-8168891-B1May 01, 2012Force10 Networks, Inc.Differential trace profile for printed circuit boards
    US-8415777-B2April 09, 2013Broadcom CorporationIntegrated circuit with millimeter wave and inductive coupling and methods for use therewith
    US-8432706-B2April 30, 2013Samsung Electro-Mechanics Co., Ltd.Printed circuit board and electro application
    US-8780584-B2July 15, 2014Samsung Electro-Mechanics Co., Ltd.Printed circuit board and electro application
    US-8848389-B2September 30, 2014Sony CorporationTransmission device and method for manufacturing same, and wireless transmission device and wireless transmission method
    US-9407997-B2August 02, 2016Invensense, Inc.Microphone package with embedded ASIC
    US-9881883-B2January 30, 2018Amit VermaElectronic device with microfilm antenna and related methods